666 スキル
Policy rules, mandatory sequence, parallel UNIT_FIX decision tree, escalation rules, and checklists for the RTL bug fix workflow. Pure reference — no orchestration.
Phase 3 uArch design using Claude Code native teams for parallel dual-stream uArch + BFM development. Manages per-block uarch design, BFM validation gate, and 5-reviewer 3-round iterative review.
Policy rules, UVM naming conventions (m_ prefix, u_dut instance), commercial simulator requirements, coverage collection rules, and checklists. Pure reference — no orchestration.
Policy for P5A functional closure. Defines hierarchy-level verification depth, coverage goals, and requirement traceability gates.
Phase 5B silicon validation for block/top signoff readiness. Runs synthesis, constraints, timing-oriented checks, and top integration precision checks after functional closure.
This skill should be used when conducting architecture review with area/performance/power tradeoff analysis. Saves review reports to reviews/ directory.
This skill should be used when developing SystemC TLM Bus Functional Models with AT non-blocking transport and AMBA protocol support from architecture block specifications.
UVM (Universal Verification Methodology) coding convention and methodology guideline skill. Covers class hierarchy, factory patterns, sequence/sequencer, TLM ports, coverage integration, and naming conventions for UVM testbenches.
Phase 3 uArch design. Concretizes P2 modules into sub-blocks with clock domains, protocol assignment, register/SRAM/FSM allocation. Validates via TLM-based BFM with per-block I/O logging.
SystemVerilog coding convention and design guideline skill. Enforces lowRISC style + project overrides for all .sv/.v file generation. Covers naming, module structure, power optimization, FPGA considerations, and pipelining for timing closure.
Passive simulation tool profiles for replayable execution (verilator, iverilog, vcs, xrun, questa).
This skill should be used when performing 3-way consistency checks between C reference model, BFM, and RTL simulation outputs.
Phase 7: Free exploration mode for algorithm alternatives, optimization experiments, and technology evaluation. Exempt from pipeline rules (Rule 9).
Policy rules, prerequisite definitions, phase gate criteria, feedback loop classification, and checklists for the Phase 4→5 pipeline. Pure reference — no orchestration.
Phase 6: Design Review & Documentation with 2-round consistency checks, detailed design notes with decision rationale, and PDF generation support.
Policy rules, SVA coding conventions, SymbiYosys engine guide, 3-round iterative refinement protocol, and formal verification checklists. Pure reference — no orchestration.
This skill should be used when proving or disproving formal properties on RTL using SymbiYosys BMC and induction. Triggers on 'formal verification', 'prove property', 'SVA'.
Verification criteria, module graduation gates, coverage targets, synthesis estimation policy, and checklists for the Phase 5 three-stage verification pipeline. Pure reference — no orchestration.
This skill should be used when completing design documents from spec through microarchitecture (Phase 1→3). Produces research artifacts, block architecture, reference model, microarchitecture specs, and BFM with full quality gates and 3-round iterative reviews — stopping before RTL implementation for human review.
This skill should be used when running Yosys synthesis for area/timing estimation, synthesizability checking, or generating SDC timing constraints. Detects inferred latches, unmapped cells, and produces Design Compiler/Genus-ready SDC.
This skill should be used when implementing RTL and running verification from existing microarchitecture documents (Phase 4→5). Requires completed Phase 1-3 artifacts as prerequisites. Produces RTL code, unit tests, and full verification with Phase 5→4 feedback loops — stopping before Design Note phase.
Policy rules, 10-Wave pipeline definitions, coding conventions, wave overlap strategy, escalation conditions, and checklists for the Phase 4 RTL implementation pipeline. Pure reference — no orchestration.
Policy rules, phase gate definitions, cascading quality protocol, handoff checklist, and ADR requirements for the Phase 1→3 pipeline. Pure reference — no orchestration.
Policy rules, coverage targets (90% line, 80% toggle, 70% FSM), gap prioritization heuristics, 3-round iterative refinement protocol, and checklists. Pure reference — no orchestration.
This skill should be used when creating minimal reproduction testbenches for RTL bugs. Isolates root cause with waveform analysis.
Policy rules, multi-seed strategy, coverage targets, signal naming conventions, traceability format, and checklists for Tier 3 module-level cocotb regression. Pure reference — no orchestration.
μArch design criteria, clock domain rules, protocol assignment rules, BFM validation requirements, signal naming conventions, and checklists for the Phase 3 μArch design pipeline. Pure reference — no orchestration.
This skill should be used when measuring RTL throughput and latency against BFM baselines. Flags deviations exceeding 10%.
Interactive tutorial for RTL Agent Team. Explains key commands, 6-Phase pipeline, domain expert extension, and team mode. Auto-detects user language; append a language name to override (e.g., /rtl-agent-team:rat-tutorial Korean).
Phase 1-3 pipeline using native teams for parallel execution within each phase. Sequences P1 research team, P2 architecture team, P3 uArch team with inter-phase quality gates.