職業

Electronics Engineers, Except Computer

666 スキル

AIに聞く

666 スキル

Rtl Ip Instantiate

This skill should be used when generating IP instantiation wrappers from IP-XACT descriptors or datasheets with convention-compliant port mapping.

babyworm12

データエンジニアリング

Rat P1p3 Spec Uarch Policy

Policy rules, phase gate definitions, cascading quality protocol, handoff checklist, and ADR requirements for the Phase 1→3 pipeline. Pure reference — no orchestration.

babyworm12

コード品質

SystemVerilog coding convention and design guideline skill. Enforces lowRISC style + project overrides for all .sv/.v file generation. Covers naming, module structure, power optimization, FPGA considerations, and pipelining for timing closure.

babyworm12

学術

Eda Research

Component research and procurement. Search JLC for components, analyze datasheets, compare options, and document selections with rationale.

l3wi11

データエンジニアリング

Domain Iotdigital Twin

Digital twin design patterns including state-based and simulation-based modeling, real-time state synchronization, predictive maintenance via simulation, what-if scenario analysis, 3D visualization, and platform guidance for Azure Digital Twins and AWS IoT TwinMaker.

rnavarych11

Electronics Engineers, Except Computer

Rtl Ip Instantiate

Rat P1p3 Spec Uarch Policy

Systemverilog

Eda Research

Domain Iotdigital Twin

Electronics Engineers, Except Computer

Rtl Ip Instantiate

Rat P1p3 Spec Uarch Policy

Systemverilog

Eda Research

Domain Iotdigital Twin

Build Sequential Circuit

Design Logic Circuit

Build Sequential Circuit

Flotherm Sim

Embedded Engineer

Scikit Rf Sim

Build Sequential Circuit

Design Logic Circuit

Volt Firmware

Volt Ota

Lars Reger Perspective

Erik Ekudden Perspective

JITX Pin Assignment

Debug Design

Optimize Ppa

Generate Sram

Jitx Component Modeler

Harness Engineering

Spectre Netlist-Mode Gotchas

Sim Sweep

Sim Run

Sim Setup

Schematic Gen

Gm Over Id

Mxl Singlemode