<Purpose> Run Yosys synthesis estimation on RTL targeting **ASIC TSMC 28nm** (approximated via NanGate45 liberty). Area is reported in **NAND2 gate equivalents** (NAND2X1 fanout-of-2, ≈ 0.798 μm² in NanGate45).

SDC-first flow: SDC constraints are generated BEFORE synthesis to ensure timing-aware optimization. Flow: 1. SDC generation → 2. sv2v conversion → 3. Yosys synthesis with NanGate45 liberty → 4. PPA report

Outputs: syn/log/ (logs), syn/rpt/ (reports), syn/vnet/ (netlist), syn/summary.json, and syn/constraints/design.sdc.

See references/yosys-commands.md for command reference and latch detection guide. See references/sdc-best-practices.md for SDC writing rules and tool-specific commands. </Purpose>

<Use_When>

RTL is lint-clean and pre-synthesis area/timing estimates are needed
Checking whether RTL is synthesizable (no latches, no unresolved references)
Comparing area impact of an RTL change
SDC timing constraints needed for Design Compiler, Genus, or OpenSTA
Pre-tapeout constraint review gate </Use_When>

<Do_Not_Use_When>

RTL has lint errors (fix with rtl-lint-check first)
Commercial synthesis tool required for signoff (Yosys is for estimation only)
Only simulation results needed </Do_Not_Use_When>

<Steps> 1. Verify RTL uses `logic` (no `reg`/`wire`) before synthesis — flag violations early <Examples> <Good> ASIC 28nm estimation (NanGate45): 12,450 cells; area 9,935 μm²; 12,450 NAND2-FO2 gate equivalents; max logic depth 18; no latches; SDC with 200MHz sys_clk constraint applied before synthesis. </Good> <Bad> Running generic synthesis (no liberty file) — area/timing estimates are meaningless without technology mapping. Skipping SDC creation — timing-unaware optimization produces unreliable PPA estimates. Ignoring Yosys latch warnings — inferred latches cause hold-time violations in silicon. Using FPGA synthesis (synth_xilinx) for ASIC estimation — wrong target technology. </Bad> </Examples> <Advanced> **Default ASIC synthesis flow (NanGate45 — TSMC 28nm proxy):** ```bash # NanGate45 is the DEFAULT and ONLY target for ASIC estimation dfflibmap -liberty NangateOpenCellLibrary_typical.lib abc -liberty NangateOpenCellLibrary_typical.lib stat -liberty NangateOpenCellLibrary_typical.lib ```

# Preferred: replayable wrapper (auto-includes rtl/common/, handles sv2v internally) syn/scripts/run_syn.sh --tool yosys --top {module} -f rtl/filelist_{module}.f --liberty NangateOpenCellLibrary_typical.lib # With commercial tool (no sv2v needed): syn/scripts/run_syn.sh --tool dc_shell --top {module} -f rtl/filelist_{module}.f # Optional: skip if tool unavailable (for non-blocking estimation) syn/scripts/run_syn.sh --tool yosys --top {module} -f rtl/filelist_{module}.f --skip-if-unavailable

yosys -p "read_verilog rtl/{module}/{module}_v2v.v; \ hierarchy -check -top {module}; proc; opt; fsm; opt; \ memory; opt; techmap; opt; \ dfflibmap -liberty NangateOpenCellLibrary_typical.lib; \ abc -liberty NangateOpenCellLibrary_typical.lib; clean; \ stat -liberty NangateOpenCellLibrary_typical.lib" \ | tee syn/log/{module}_synth.log

# ============================================================ # Step 2: SDC Generation (MANDATORY — before synthesis) # ============================================================ Task(subagent_type="rtl-agent-team:constraint-writer", prompt="Generate comprehensive SDC for design top module. Read requirements.json for clock frequencies, docs/phase-3-uarch/*.md for multicycle paths, RTL top-level for port list. Use templates/design-constraints.sdc as scaffold. Write syn/constraints/design.sdc with: create_clock for all clocks using {domain}_clk naming, set_input_delay/set_output_delay for all i_*/o_* ports, set_false_path for async resets with justification, set_multicycle_path (both -setup and -hold) from uarch pipeline specs, design rules (set_max_fanout, set_max_transition). Validate with tclsh. See references/sdc-best-practices.md for rules.") # ============================================================ # Step 3-4: ASIC Synthesis Estimation via wrapper (NanGate45 / TSMC 28nm proxy) # ============================================================ Task(subagent_type="rtl-agent-team:eda-runner", prompt="Run ASIC synthesis estimation using wrapper: syn/scripts/run_syn.sh --tool yosys --top {top} -f rtl/filelist_top.f --liberty NangateOpenCellLibrary_typical.lib --skip-if-unavailable. Script handles sv2v conversion internally. Outputs: syn/rpt/ (reports), syn/vnet/ (netlist), syn/log/ (logs). Check output for inferred latches. If SKIPPED, record status.") # ============================================================ # Step 6-9: Parse results → gate count (NAND2-FO2 equivalent) # ============================================================ Task(subagent_type="rtl-agent-team:synthesis-reporter", prompt="Parse syn/log/ and syn/rpt/ Yosys output. Extract cell count, area (um2), compute NAND2-FO2 gate count (area / 0.798). Flag any inferred latches as hard errors. Write syn/summary.json with gate_count_nand2 field. Technology: ASIC TSMC 28nm (NanGate45 proxy).")

Cell	Concern
`$_DFF_*`	Normal flip-flops (count should match intent)
`$_DLATCH_*`	CRITICAL — must be zero
`$_MUX_`	High count may indicate priority encoding
`$add`, `$mul`	Check if area-efficient implementation needed
`$mem`	Check if SRAM inference was intended

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