電子工程師（電腦除外）

Spectre Netlist-Mode Gotchas

Critical Spectre netlist-mode gotchas for standalone simulation (no Virtuoso ADE). Use when: (1) writing Spectre testbench .scs files with `simulator lang=spectre`, (2) noise analysis shows absurd values (megavolts of noise) — oprobe topology is wrong, (3) SFE-30 error on `ac=1` in vsource — use `mag=1` in native Spectre lang, (4) SFE-1997 error on `oprobe=<node_name>` — must be a circuit element not a node, (5) parsing PSF ASCII output from Spectre (dc_op.dc, ac_gain.ac, noise_an.noise), (6) phase margin calculation for inverting amplifier topologies, (7) slew rate measurement gives wrong result with small-signal step — need large signal, (8) ICMR from DC sweep — use transistor region fields, not CM gain (which is ≈ 0), (9) SFE-868 from ADE-generated netlist — oa/lib/../ model path only works in ADE interactive mode.

Sim Sweep

Run parameter sweeps and PVT corner simulations on Virtuoso. Use when sweeping design variables, running corner analysis, or characterizing circuits across operating conditions.

計算化學

Sim Run

Run circuit simulation (DC, tran, AC) on Virtuoso. Use when executing Spectre simulation, running analysis, or checking simulation results.

雲端

Sim Setup

Set up Virtuoso simulation with Ocean SKILL. Use when configuring simulator, design target, model files, or design variables before running simulation.

商業應用

Schematic Gen

Generate Virtuoso schematics from topology descriptions via vcli schematic commands. Use when: (1) user wants to draw/create a schematic in Virtuoso, (2) user says "draw the OTA" or "create the schematic", (3) after sizing is complete and ready to build the circuit, (4) user provides a topology and wants it instantiated.

實驗室工具

Gm Over Id

gm/Id methodology for analog IC design — transistor sizing via lookup table approach. Use when designing amplifiers, current mirrors, OTAs, or any analog circuit where you need to determine W/L from specs (GBW, gain, noise). Also use when the user mentions gm/id, transistor sizing, Vov, current density, or design space exploration.

計算化學

Mxl Singlemode

This skill should be used when users need the MaxwellLink single-mode cavity solver for fast prototyping and regression, in either socket or embedded mode.

TaoELi7

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Rtl Ip Instantiate

This skill should be used when generating IP instantiation wrappers from IP-XACT descriptors or datasheets with convention-compliant port mapping.

babyworm12

數據工程

Rat P1p3 Spec Uarch Policy

Policy rules, phase gate definitions, cascading quality protocol, handoff checklist, and ADR requirements for the Phase 1→3 pipeline. Pure reference — no orchestration.

babyworm12

代碼質素

Systemverilog

SystemVerilog coding convention and design guideline skill. Enforces lowRISC style + project overrides for all .sv/.v file generation. Covers naming, module structure, power optimization, FPGA considerations, and pipelining for timing closure.

babyworm12

學術

Eda Research

Component research and procurement. Search JLC for components, analyze datasheets, compare options, and document selections with rationale.

l3wi11

數據工程

Domain Iotdigital Twin

Digital twin design patterns including state-based and simulation-based modeling, real-time state synchronization, predictive maintenance via simulation, what-if scenario analysis, 3D visualization, and platform guidance for Azure Digital Twins and AWS IoT TwinMaker.

rnavarych11

Build Sequential Circuit

Build sequential (stateful) logic circuits including latches, flip-flops, registers, counters, and finite state machines. Covers SR latch, D and JK flip-flops, binary/BCD/ring counters, and Mealy/Moore FSM design with clock signal and timing analysis. Use when a circuit must remember past inputs, count events, or implement a state-dependent control sequence.

Design Logic Circuit

Design combinational logic circuits from a functional specification through gate-level implementation. Covers AND, OR, NOT, XOR, NAND, NOR gates; NAND/NOR universality conversions; and standard building blocks including multiplexers, decoders, half/full adders, and ripple-carry adders. Use when translating a Boolean function or truth table into a hardware-realizable gate network and verifying it by exhaustive simulation.

Build Sequential Circuit

ラッチ、フリップフロップ、レジスタ、カウンタ、有限状態機械を含む順序（ステートフル）論理回路を構築する。SRラッチ、DおよびJKフリップフロップ、バイナリ/BCD/リングカウンタ、クロック信号とタイミング分析を伴うMealy/Moore FSM設計をカバーする。回路が過去の入力を記憶する必要がある時、イベントをカウントする時、状態依存の制御シーケンスを実装する時に使用する。

雲端

Flotherm Sim

Use when running Simcenter Flotherm thermal cases through the sim runtime. Primary path is GUI automation via pywinauto UIA (`.pack` import + FloSCRIPT playback). Direct batch (`translator.exe` + `solexe.exe`) is a headless optimization for re-solving existing projects only.

svd-ai-lab10

框架內部結構

Embedded Engineer

Embedded/IoT Engineer — Arduino/ESP32/Raspberry Pi, sensor integration, MQTT/BLE/LoRa, firmware development, battery optimization

aiunlocked141210

Scikit Rf Sim

Use when driving scikit-rf (Python RF / microwave network analysis library) via Python scripts — Touchstone (.s2p / .snp) I/O, S-parameter network manipulation, transmission-line and ABCD-matrix media, calibration (SOLT / TRL), time-gating, plotting on Smith chart — through sim runtime one-shot execution.

svd-ai-lab10

項目管理

Build Sequential Circuit

Construir circuitos lógicos secuenciales (con estado) incluyendo latches, flip-flops, registros, contadores y máquinas de estados finitos. Cubre latch SR, flip-flops D y JK, contadores binarios/BCD/anillo y diseño de FSM Mealy/Moore con análisis de señal de reloj y temporización. Usar cuando un circuito debe recordar entradas pasadas, contar eventos o implementar una secuencia de control dependiente del estado.

Design Logic Circuit

Entwerfen combinational logic circuits from a functional specification durch gate-level implementation. Umfasst AND, OR, NOT, XOR, NAND, NOR gates; NAND/NOR universality conversions; and standard building blocks including multiplexers, decoders, half/full adders, and ripple-carry adders. Verwenden wenn translating a Boolean function or truth table into a hardware-realizable gate network and verifying it by exhaustive simulation.

Backend

Volt Firmware

Produce a complete firmware architecture spec for a described device — layer diagram, module responsibilities, HAL interface definitions, key state machines, RTOS decision. Use when asked to "design firmware architecture", "plan embedded firmware", "architect an IoT device", "how should I structure this firmware", or given a device description and asked what the firmware should look like.

tonone-ai10

銷售同市場推廣

Volt Ota

Produce a complete OTA update system design — partition layout, update flow, rollback conditions, validation checks, fleet management approach, failure modes and recovery. Use when asked about "OTA updates", "firmware updates over the air", "how do I update devices in the field", "OTA strategy", or "remote firmware update design".

tonone-ai10

Lars Reger Perspective

Lars Reger的思维框架与表达方式。基于 10 个数据来源，提炼 0 个核心心智模型、0 条决策启发式和完整的表达 DNA。用途：作为思维顾问，用 Lars Reger 的视角分析 Tech 问题。触发词（中）：「用 Lars Reger 的视角」「如果 Lars Reger 会怎么看」「切换到 Lars Reger 模式」 Triggers (EN): "Use Lars Reger's perspective", "What would Lars Reger think?", "Switch to Lars Reger mode"

ekcheungAI8

Erik Ekudden Perspective

Erik Ekudden的思维框架与表达方式。基于 11 个数据来源，提炼 2 个核心心智模型、0 条决策启发式和完整的表达 DNA。用途：作为思维顾问，用 Erik Ekudden 的视角分析 Tech 问题。触发词（中）：「用 Erik Ekudden 的视角」「如果 Erik Ekudden 会怎么看」「切换到 Erik Ekudden 模式」 Triggers (EN): "Use Erik Ekudden's perspective", "What would Erik Ekudden think?", "Switch to Erik Ekudden mode"

ekcheungAI8

JITX Pin Assignment

This skill should be used when the user asks about "provide/require patterns", "@provide.one_of" or "@provide.subset_of" decorators, "programmatic Provide", "pin muxing" (MCU peripherals on shared pins), "DiffPair P/N polarity swapping", "PCIe lane swapping" or width variants, "DDR4 byte/bit swapping", "LPDDR5 channel swapping", "hierarchical provider composition", topology (>>) on pin-assigned ports, ConstrainDiffPair or ConstrainReferenceDifference with provide/require, or "flexible pin mapping" for FPGAs and MCUs. Covers provide, Provide, require, all_of, one_of, subset_of, and protocol-specific pin flexibility with SI constraints.

JITx-Inc8