Electronics Engineers, Except Computer

Tools Pipeline Patterns

Design internal tools and content pipelines that reduce manual work and make authoring safer.

MRCalderon3D15

프레임워크 내부 구조

Ros2 Robotics

Patterns for developing robotics applications with ROS2 (Robot Operating System 2). Covers nodes, topics, services, actions, launch files, lifecycle management, real-time considerations, and common pitfalls. Use when ", " mentioned.

Supraforge14

프레임워크 내부 구조

Fpga Design

Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.

Supraforge14

스크립팅

Arm Cortex Microcontrollers

Automatically converted skill for arm-cortex-microcontrollers

Supraforge14

디버깅

Bfd Debug Interface

Use when debugging STM32 applications with J-Link or ST-Link, including breakpoints, watchpoints, register or memory inspection, HardFault analysis, and automated fault-context capture.

디버깅

Bfd Ioc Parser

Use when parsing STM32CubeMX .ioc files to extract hardware configuration and generate structured JSON outputs for review or downstream analysis.

실험실 도구

Bfd Register Capture

Use when sampling STM32 peripheral registers, tracking register changes over time, or exporting register snapshots to CSV for hardware-state analysis.

테스팅

Bfd Fault Logger

Use when recording STM32 hardware faults such as HardFault, BusFault, and UsageFault, then exporting structured fault reports.

디버깅

Bfd Debug Orchestrator

Use when running end-to-end STM32 debug campaigns that coordinate flash, RTT, register capture, HardFault snapshots, and error archival across multiple tools.

패키지 및 배포

Stm32 Development Workflow

STM32通用程序开发完整流程，基于STM32CubeCLT命令行工具链。涵盖工具链安装、 HAL库配置、项目构建、固件编译和ST-Link烧录。适用于STM32F1/F4/H7等系列，解决编译错误、链接错误、烧录失败等常见问题。

EricSun78713

생산성 및 통합

Kicad Pcb

Control KiCAD for electronic circuit design, schematic creation, and PCB layout operations

pacphi12

Rat P1p3 Spec Uarch

This skill should be used when completing design documents from spec through microarchitecture (Phase 1→3). Produces research artifacts, block architecture, reference model, microarchitecture specs, and BFM with full quality gates and 3-round iterative reviews — stopping before RTL implementation for human review.

Git 워크플로

Rtl P4s Bugfix Policy

Policy rules, mandatory sequence, parallel UNIT_FIX decision tree, escalation rules, and checklists for the RTL bug fix workflow. Pure reference — no orchestration.

Rtl P6 Design Review

Phase 6: Design Review & Documentation with 2-round consistency checks, detailed design notes with decision rationale, and PDF generation support.

코드 품질

Rtl Silicon Validation Policy

Policy for P5B silicon validation. Defines block/top synthesis, constraints quality, timing-oriented checks, and signoff readiness criteria.

Rtl P5s Uvm Policy

Policy rules, UVM naming conventions (m_ prefix, u_dut instance), commercial simulator requirements, coverage collection rules, and checklists. Pure reference — no orchestration.

Rat Tutorial

Interactive tutorial for RTL Agent Team. Explains key commands, 6-Phase pipeline, domain expert extension, and team mode. Auto-detects user language; append a language name to override (e.g., /rtl-agent-team:rat-tutorial Korean).

CI/CD

Rat P4p5 Impl Verify Policy

Policy rules, prerequisite definitions, phase gate criteria, feedback loop classification, and checklists for the Phase 4→5 pipeline. Pure reference — no orchestration.

Rat Auto Design

This skill should be used when starting a full RTL design pipeline from spec to verification. Orchestrates 6-phase flow (Research → Architecture → μArch → RTL → Verify → Design Note) with dual-layer phase gates and hierarchical spec compliance.

CI/CD

Rat P1p3 Spec Uarch Team

Phase 1-3 pipeline using native teams for parallel execution within each phase. Sequences P1 research team, P2 architecture team, P3 uArch team with inter-phase quality gates.