Use this skill for SAR ADC system design and all its key building blocks. Covers: SAR ADC architecture, CDAC operation and switching schemes, sync/async SAR logic, top-plate vs bottom-plate sampling, noise and ENOB budgeting, redundancy, PVT, metastability, peripheral design, and Verilog-A modeling. Also covers the core analog submodules needed for a complete SAR ADC: StrongArm dynamic comparator (topology, noise, offset, sizing), bootstrapped sampling switch (circuit operation, Ron flatness, sizing), and LDO regulator for clean ADC supply (topology, PSRR, compensation, sizing). Includes the SAR_11B_ZZS taped-out 11-bit reference design (TSMC 28nm HPC+). Also covers Spectre simulation setup, ENOB/SNDR measurement with ADCToolbox, and a phased verification flow (behavioral → hybrid → full transistor-level). Use for any question about SAR ADC design from specs to first-order block decisions, submodule sizing guidance, simulation/verification, or reference design lookup.
This skill is a compact engineering guide built from the raw_materials/ course set.
Use it for:
Use only the minimum reference needed for the user task:
references/core-architecture.md
Use for SAR operation, residue intuition, CDAC-centered architecture, comparator role, and the practical meaning of sync versus async timing.
references/design-and-tradeoffs.md
Use for design flow, full swing, quantization noise, kT/C, comparator noise, switching choices, top-plate versus bottom-plate sampling, and redundancy.
references/robustness-and-system.md
Use for PVT, Monte Carlo interpretation, metastability, BER, reference strategy, input path, supply design, and shippable-product concerns.
references/comparator.md
Use for StrongArm dynamic comparator topology, four operating phases, transistor
sizing, noise (probit method, σ formula), offset sources, speed/power/noise
trade-offs, and FOM.
references/bootstrap_switch.md
Use for bootstrapped sampling switch topology, gate voltage derivation, transistor
roles, sizing rules (CB ≥ 5×Cgg), Ron flatness, clock feedthrough, and comparison
to plain NMOS/CMOS switch.
references/ldo.md
Use for LDO supply design in SAR ADC context: PMOS-pass topology, Miller
compensation, sizing from specs, loop gain/PSRR/noise formulas, and
compensation trade-offs.
references/sar-logic.md
Use for SAR logic implementation: full conversion timing, sync vs async state
machine, async latch chain (L5_LATCH_CELL transistor roles, NOR3/NAND2 control
logic, ENB chain), complementary pass-gate DAC switch polarity convention,
DFF output latching, and Verilog-A behavioral model correspondence. Based on
the taped-out SAR_11B_ZZS (TSMC 28nm HPC+).
references/sar-adc-11b-zzs.md
Use for the taped-out 11-bit fully differential SAR ADC reference design:
TSMC 28nm HPC+, 0.9V, bootstrap switch, CDAC unit cap 200 aF, StrongArm
comparator, async logic. Module reference table and quick sizing lookup.
references/simulation-and-verification.md
Use for SAR ADC Spectre simulation setup: coherent sampling, input signal
conventions, sync vs async clocking, strobe resampling, ENOB/SNDR/SFDR
extraction with ADCToolbox, debugging common failures (comparator polarity,
bus ordering, charge injection, sampling alignment), differential vs
single-ended CDAC tradeoffs, and the phased verification flow.
For design questions, follow this order:
The skill already includes baseline models in assets/va/:
L2_cdac_4b_ideal.vaL2_comparator_ideal.vaL2_logic_4b_sync.vaL3_logic_4b_async.va_va_dac_4b.va_va_dac_4b_se.vasar_4b_se_ideal.vaUse these as starting points for behavioral verification and system integration.
spectre or virtuoso skills alongside the submodule references in this skill.