Electronics Engineers, Except Computer

Bug Report

自动解析环境分析文档中的 RTL_BUG 属性，生成 Bug 报告框架（04_{DUT}_bug_report.md），LLM 填写根因分析和修复建议。

전산화학

Functional Spec

提取和分析被测模块(DUT)的功能规格和形式化检测点

Coverage Optimization

指导解释覆盖率报告并优化未覆盖死角的技能

코드 품질

Env Generation

Formal 验证环境（Checker & Bind Wrapper）的配置与构建指南

코드 품질

Sva Property Generation

基于 SVA 规范编写属性检测代码

Counterexample Testgen

自动解析环境分析文档和 wrapper.sv，为每个 RTL_BUG 生成 Python 测试函数框架，LLM 填写引脚驱动和断言逻辑。

보안

Iot Architect

Expert in IoT system design, hardware selection (ESP32, LoRa), and firmware architecture (Arduino, PlatformIO). Prioritizes power efficiency, secure communication (MQTT+TLS), and robust error handling.

NeverSight117

영업 및 마케팅

Vivado Implementation Decision Guide

$37

Shinei-Nouzen-Arch116

Vivado Programming & Debugging Guide

Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation, mark_debug attribute and debug probing flows (Netlist Insertion, HDL Instantiation), Set Up Debug Wizard, ILA cross-trigger architecture, debug core timing impact and mitigation, Vivado Hardware Manager operation, FPGA/SoC device programming, Versal debugging architecture (AXI4 Debug Hub, CIPS integration), SVF file programming, debug clock requirements, and common debug error troubleshooting. This skill provides debugging strategy and decision-making knowledge — for TCL command execution use vivado-tcl, for implementation strategies use vivado-impl, for timing analysis use vivado-analysis.

Shinei-Nouzen-Arch116

IDE 플러그인

Vitis Hls Synthesis

Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.

Shinei-Nouzen-Arch116

게임 개발

Circuit Fibsqrt

Guide for implementing combinational/sequential logic circuits using gate-level descriptions in text-based simulators. This skill applies when building circuits for mathematical functions like integer

lazyFrogLOL100

시스템 관리

Monitored Subtask Execution

Monitored single-subtask execution workflow. Use the repository MCP service `corobot_mcp_server` to start, monitor, stop, and reset one prompt-driven robot rollout through the sequence `set_evaluate_params`, poll `get_status`, then `stop/reset`. Use this skill whenever a larger workflow needs one repeatable, safe execution unit with timeout handling and deterministic cleanup.

RoboClaw-Robotics85

프로젝트 관리

Eap Data Collection

EAP data collection workflow for prompt-driven robotic rollouts. Use this skill when you need to collect self-resetting forward and reverse trajectory pairs, keep rollout metadata and trajectory records in dataset `D`, and delegate each robot execution step to $monitored-subtask-execution so MCP startup, monitoring, timeout handling, stop, and reset remain centralized.

RoboClaw-Robotics85

스크립팅

Long Horizon Execution

Long-horizon robot task execution workflow for multi-step manipulation tasks. Use this skill when one user goal must be decomposed into ordered subtasks, each subtask needs explicit success checks, retries, or recovery, and every prompt-driven policy rollout should be executed through $monitored-subtask-execution instead of calling raw MCP robot tools directly.

RoboClaw-Robotics85

머신러닝

EMC Pre-Compliance Skill

EMC pre-compliance risk analysis for KiCad PCB designs — 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, shielding, and magnetic leakage from switching inductors. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".

hashgraph-online75

KiCad Project Analysis Skill

Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Every finding carries a confidence label and evidence source with trust_summary rollup. Analyzes PDF schematics from dev boards, reference designs, eval kits, and datasheets. Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb, .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal tracing, power budget, DFM, or wants to understand, debug, compare, or review any hardware design. Also for "check my board", "review before fab", "what's wrong with my schematic", "is this ready to order", "check my power supply", "verify this circuit", or any electronics/PCB design question.

hashgraph-online75

ngspice Simulation Skill

ngspice simulation tutorial and template skill. Provides nine standard simulation examples: (1) Transient — RC charging voltage and current; (2) DC — NMOS Id-Vds family curves; (3) AC — RC low-pass filter frequency response; (4) Noise — RC filter output noise spectral density and kT/C; (5) Transient — sample-and-hold switch comparison; (6) Transient — kT/C noise time-domain statistical measurement; (7) DC — NMOS current mirror output characteristics; (8) AC — common-source amplifier frequency response; (9) DC — transmission gate on-resistance. Built-in PTM 180/45/22nm models included.

Arcadia-175

머신러닝

Transistor Models

Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads required after installing this skill. Independent of the gmoverid skill — can be used directly in any ngspice/HSPICE project.

Arcadia-175

금융 및 투자

Architecture

Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. Use when evaluating design candidates, estimating power/area/performance, assessing technical risk, or producing a microarchitecture document for handoff to RTL design.

프로젝트 관리

Physical Design

Full physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off. Use when implementing a gate-level netlist through to GDS-II, closing timing and power, or performing any individual PD stage analysis.

도메인 및 DNS 도구

Memory Keeper

Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for any chip-design domain. Run after every 10 orchestrator sessions, or on demand when a domain has collected new issue/fix patterns.

Sta

Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure. Use when running timing analysis on a design, reviewing timing violations, guiding ECO fixes, or performing timing sign-off for tape-out.

실험실 도구

Infrastructure

EDA tool detection, wrapper deployment, and MCP configuration for digital chip design environments. Use when setting up a new workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.

머신러닝

Hls

High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification. Use when converting C/C++ to synthesisable RTL, optimising for latency/throughput/area targets using pragmas, or verifying that generated RTL matches the golden C model.

테스팅

Formal Verification

Formal property verification (FPV) and logical equivalence checking (LEC). Use when proving design properties exhaustively, checking RTL vs gate-level netlist equivalence, verifying CDC crossings formally, or closing verification coverage gaps that simulation cannot efficiently reach.

아키텍처 패턴

Dft

Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan. Use when planning a DFT strategy, inserting scan, generating test patterns, or verifying that a chip will be testable in manufacturing.