Computerchemie
LDO Skill — PTM 180nm Low Dropout Regulator
PTM 180nm PMOS-pass LDO regulator simulation, sizing, and analysis skill. Use this skill whenever the user wants to: (1) simulate or re-run LDO DC/AC/noise/transient analyses in ngspice, (2) plot loop gain, PSRR, output impedance, load-step response, noise PSD, or transistor operating points, (3) compute or verify initial transistor sizing from specs (Vin, Vout, Iload, Cload, Vref), (4) iteratively adjust device sizes to meet specs (output accuracy ±1%, phase margin, PSRR, load/line regulation, noise, offset), (5) apply theoretical formulas for GBW, zero/pole frequencies, PSRR, load regulation, noise, or offset, (6) perform trade-off analysis between competing specs, (7) learn LDO topology, compensation theory, or sizing methodology. Technology: PTM 180nm BSIM3v3 (NMOS/PMOS, Lmin=180nm, Wmin=220nm, VDD up to 3.3V). Requires: ngspice on PATH, Python 3 + numpy/matplotlib/scipy.