Schematic Intelligence

• From Altium: File → Export → Netlist → Protel → exports .NET file.
• From Altium: Reports → Bill of Materials → export as CSV or Excel.
• Optionally: File → Smart PDF → exports multi-page schematic PDF.
• Load references/altium-netlist-format.md for exact export format details and version variations.

Reference Guide

Bundled Scripts

Dependencies: standard library only (no pip packages required)

Constraints

MUST DO

• Always work from the exported netlist — do not attempt to parse binary Altium .SchDoc files.
• Flag every net with only one connected pin as a potential floating net warning.
• Identify power nets by name pattern (GND, VCC, VDD, 3V3, 5V, VBAT, AGND, DGND, etc.) and report them separately.
• Group nets that share a name prefix into logical buses (e.g., all SPI_* nets form the SPI bus).
• Report component count by type using standard ref-des prefix conventions (R=resistor, C=capacitor, U=IC, Q=transistor, D=diode, J/P=connector, L=inductor, T=transformer, SW=switch).

MUST NOT DO

• Infer component function from ref-des prefix alone — always cross-reference with value/description from netlist or BOM.
• Declare a net as an error without context — some single-pin nets are intentional (test points, guard rings).
• Assume net name uniqueness across sheets without checking for sheet-scope vs. global net declarations.
• Present raw net lists without grouping — always aggregate into functional blocks for readability.
• Confuse pin numbers with net names — a pin reference like U1-14 means component U1, pin 14, not a net.

Output Template

For schematic analysis tasks, report:

1. Project summary: component count (total and by type), net count, sheet count.
2. Power distribution: supply nets detected, components on each rail, estimated current paths.
3. Functional blocks: name, components, supply rail, external interfaces (nets connecting to other blocks).
4. IC interconnections: structured list of which ICs share nets and what functions those nets carry.
5. Bus groups: name, member nets, connected components.
6. Design rule warnings: floating nets, single-pin nets, unconnected pins (NC markers), duplicate RefDes.
7. Hierarchy (if multi-page): sheet names, hierarchical block instances, cross-sheet net connections via ports.

Primary References

• Altium Designer Documentation — Netlist export and hierarchical design
• IEC 60617 — Graphical Symbols for Diagrams (standard component symbols)
• Cadence Allegro / OrCAD netlist format — comparison reference for net format variations