RTL synthesis and formal preparation using Yosys. Use when working with DV Flow yosys.* tasks, writing .ys synthesis scripts, interpreting Yosys logs and stat output, mapping designs to FPGA or ASIC cell libraries, or preparing designs for formal verification with sby/smtbmc.
Yosys is an open-source RTL synthesis framework. It reads Verilog or SystemVerilog, performs a configurable sequence of optimisation passes, maps the result to a target technology (FPGA or ASIC cell library), and writes netlists in multiple formats (JSON, Verilog, BLIF, EDIF, RTLIL, SMT2).
This skill covers three entry points:
yosys.*) – YAML-configured, data-flow-driven synthesis.ys files) – imperative command sequencesyosys.*)All tasks live in the yosys DV Flow package. Import it and connect tasks
with needs edges. RTL sources flow via standard std.FileSet filetypes;
cell libraries flow via the libertyLib filetype.