Physical Design

• OpenROAD / ORFS (make DESIGN_CONFIG=./designs/<platform>/<design>/config.mk) — full PD pipeline; executes sequentially (see sequential flow note below)
• LibreLane / OpenLane 2 (openlane <config.json>) — sequential PD pipeline built on OpenROAD; (see sequential flow note below)
• KLayout (klayout) — DRC, LVS, and GDS-II viewing/editing; used for signoff DRC in open-source flows

Proprietary

• Cadence Innovus (innovus) — floorplan through signoff; interactive and batch modes
• Synopsys IC Compiler 2 (icc2_shell) — hierarchical PD with Fusion technology
• Siemens Aprisa — physical implementation for advanced nodes

Sequential Flow Log Review (OpenROAD / LibreLane)

OpenROAD Flow Scripts (ORFS) and LibreLane execute the entire PD pipeline in a single invocation. Stages run sequentially without pausing for agent intervention. After the run completes (or fails mid-stage), the agent must read the per-stage log files to evaluate QoR and apply loop-back logic.

ORFS log layout:

logs/<platform>/<design>/
  1_1_yosys.log         # synthesis (Yosys)
  2_1_floorplan.log     # floorplan (OpenROAD)
  3_1_place.log         # global placement (OpenROAD)
  3_4_resizer.log       # resizer / timing-driven placement
  4_1_cts.log           # clock tree synthesis (OpenROAD)
  5_1_route.log         # global routing (OpenROAD)
  5_3_fillcell.log      # filler cell insertion
  6_1_finishing.log     # signoff: DRC (KLayout/Magic), LVS (Netgen), final STA

Invocation: make DESIGN_CONFIG=./designs/<platform>/<design>/config.mk Resume from stage: make do-<stage> (e.g. make do-3_2_place)

LibreLane (OpenLane 2) log layout:

runs/<design>/<run_tag>/logs/
  synthesis/            # Yosys synthesis logs
  floorplan/            # OpenROAD floorplan logs
  placement/            # OpenROAD placement logs (global + detail)
  cts/                  # OpenROAD CTS logs
  routing/              # OpenROAD global + detailed routing (DRT) logs
  signoff/              # Magic/Netgen DRC+LVS, OpenSTA final timing

Invocation: openlane <config.json> (or python3 -m openlane <config.json>) Resume from step: openlane --from <step_name> <config.json>

Agent procedure after run:

1. Identify the last successfully completed stage from log timestamps or exit codes
2. Read the log for each completed stage and extract the relevant QoR metrics (WNS, DRC count, congestion, IR drop) defined in the ## Stage: sections below
3. Apply loop-back rules from this skill; correct the input config or constraints
4. Re-invoke from the failed stage using the resume command above

Stage: floorplan

Domain Rules

1. Core utilisation target: 70–80% — leave margin for routing congestion
2. Macros: place at die edges or corners with halos (typically 5–10 μm)
3. IO pads: distribute evenly; match package pin assignment
4. Power grid: VDD/VSS straps every N rows (technology-node specific)
5. Blockages: hard blockages around analog/RF macros
6. Aspect ratio: keep close to 1:1 unless package constrains otherwise
7. Voltage island boundaries must align to row boundaries

QoR Metrics to Evaluate

• Estimated congestion (H and V): flag if > 80%
• Estimated WNS from floorplan-stage STA: flag if < −2 ns
• IR drop estimate: flag if > 10% of VDD

Output Required

• Floorplan DEF (floorplan.def)
• Power grid DEF or script
• Macro placement report
• Estimated congestion map

Stage: placement

Domain Rules

1. Sequence: global → legalise → detailed → pre-CTS optimisation
2. Pre-CTS timing: ideal clocks; uncertainty = skew + jitter estimate
3. Max utilisation per partition: 80%
4. High-fanout nets: buffer before placement or apply constraints
5. Timing-critical paths: co-locate related cells with placement constraints
6. Scan chains: re-order after placement for minimum wirelength

QoR Metrics to Evaluate

• Pre-CTS WNS: > −0.3 ns
• Cell density hotspots: flag if any region > 90%
• Estimated routing congestion overflow: flag if > 1%

Output Required

• Placed DEF
• Pre-CTS timing report (setup and hold)
• Cell density and congestion report

Stage: cts

Domain Rules

1. Target skew: < 100 ps (or per SDC set_clock_uncertainty)
2. Max transition on clock nets: per technology DRC rule (150–200 ps)
3. Max fanout per clock buffer: per library (16–32)
4. Useful skew: only with explicit sign-off approval
5. Clock gating: integrate into CTS; verify enable pin timing
6. Multi-clock: handle each domain independently; check CDC after CTS

QoR Metrics to Evaluate

• Global skew per domain: flag if > 150 ps
• Max insertion delay: flag if > 500 ps
• Post-CTS WNS (setup): flag if < −0.2 ns
• Post-CTS hold slack: must be ≥ 0 before routing

Output Required

• Post-CTS DEF
• Clock tree report (skew, insertion delay per domain)
• Post-CTS timing report (setup and hold)

Stage: routing

Domain Rules

1. Sequence: global → track assignment → detailed → search-and-repair
2. Follow foundry DRC deck (spacing, width, via enclosure)
3. Shield critical clock and analog nets
4. Upper metals for power, lower metals for signals
5. Antenna rules: insert diodes or use jump-via strategy
6. Double/multi-patterning (7 nm and below): resolve same-colour violations

QoR Metrics to Evaluate

• DRC violations: 0 at sign-off
• LVS errors: 0 at sign-off
• Post-route WNS: flag if < 0
• Routing overflow: 0

Output Required

• Routed DEF
• DRC report
• LVS report
• Post-route timing report

Stage: timing_optimization

Domain Rules

1. Multi-corner: SS (setup), FF (hold), TT (typical)
2. Setup: upsize drivers, insert repeaters, retime registers
3. Hold: insert HVT delay buffers
4. Vt swapping: SVT/LVT for speed-critical; HVT for power-insensitive paths
5. ECO: formal ECO → place in reserved sites → re-route ECO nets
6. Do not modify scan chain order without DFT approval
7. Apply POCV/AOCV per foundry sign-off agreement

QoR Metrics to Evaluate

• WNS: ≥ 0 all corners
• TNS: = 0 all corners
• Hold slack: ≥ 0 after fixing
• ECO cell count: flag if > 2% of total cells

Output Required

• Timing closure report (all corners)
• ECO change list
• SPEF
• Updated routed DEF (post-ECO)

Stage: power_optimization

Domain Rules

1. Dynamic: clock gating insertion, operand isolation, multi-Vt swapping
2. Leakage: swap non-critical cells to HVT; verify timing after each batch
3. Power domains: validate UPF (isolation, level-shifters, retention regs)
4. Voltage islands: verify IR drop per domain
5. Always-on logic: verify correct library cells
6. Power gating: verify wakeup/shutdown sequences before routing changes

QoR Metrics to Evaluate

• Total power: within spec budget
• Leakage: flag if > 15% of total at TT corner
• IR drop: < 5% VDD across all domains
• Post-power-opt WNS: must remain ≥ 0

Output Required

• Power analysis report (dynamic + static, per domain)
• IR drop report
• Updated DEF (post-power-opt)
• UPF compliance report

Stage: area_optimization

Domain Rules

1. Remove redundant buffers and inverter pairs
2. Downsize non-timing-critical cells to minimum drive strength
3. Reclaim unused standard cell sites
4. Do not drop WNS margin below 50 ps buffer
5. Re-run DRC after any area ECO

QoR Metrics to Evaluate

• Core utilisation: target 70–80%; hard limit 85%
• WNS: must remain ≥ 0
• DRC: must remain clean

Output Required

• Area utilisation report (pre vs post)
• Updated DEF
• Cell count breakdown

Stage: signoff

Sign-off Pass Criteria (all must pass)

Domain Rules

1. STA sign-off: run all required PVT corners with POCV/AOCV
2. DRC: foundry-approved deck — zero violations
3. LVS: netlist vs layout — zero errors
4. ERC: electromigration and IR drop sign-off
5. Final GDS: merge all layers, add seal ring, chip-level DRC

Failure Escalation

• Timing fail → timing_optimization
• DRC/LVS fail → routing
• Power/EM fail → power_optimization

Output Required

• Sign-off STA report (all corners)
• DRC clean report
• LVS clean report
• Final GDS-II
• Completed tape-out checklist

Memory

Write on stage completion

After each stage completes (regardless of whether an orchestrator session is active), write or overwrite one JSON record in memory/pd/experiences.jsonl keyed by run_id. This ensures data is persisted even if the flow is interrupted or called without full orchestrator context.

Use run_id = pd_<YYYYMMDD>_<HHMMSS> (set once at flow start; reuse on each stage update). Set signoff_achieved: false until the final sign-off stage completes.