Ip Architect

When asked to create or modify an IP core:

• VLNV: Define the Vendor, Library, Name, and Version (default vendor: user, library: ip).
• Interfaces: Identify Clocks, Resets, and Bus Interfaces (AXI4L, AVALON_MM, AXI4S).
• Generic/Parameters: Define configurable HDL parameters.
• Port Mapping: Map logical signals to physical HDL ports.

2. Generate .mm.yml (Memory Map Specification)

When designing a register map:

• Address Blocks: Organize registers into logical 4K/1M blocks.
• Registers: Standard width is 32 bits. Use offsets that are word-aligned (e.g., 0x0, 0x4, 0x8).
• Bit Fields: Define descriptive name, offset, width, and access type (read-write, read-only, write-1-to-clear).
• Enum Values: Provide human-readable names for specific bit combinations.

SCHEMAS & TEMPLATES

• Base Directory: ipcraft-spec/schemas/
• Schemas: ip_core.schema.json, memory_map.schema.json
• Generated Output: IPCraft uses Nunjucks templates in src/generator/templates/ to produce VHDL and vendor-specific files (Altera .tcl, AMD .xml).

WORKFLOW

1. Requirement Analysis: If the description is vague, ask for:
   • Target bus type (AXI-Lite, Avalon).
   • Data width (usually 32).
   • Specific registers needed.
   • Interrupt requirements.
2. Draft Structure: Propose a register map table first for user approval.
3. Generate YAML: Produce documented, schema-compliant YAML blocks.
4. Validation: Explicitly state that the design is word-aligned and collision-free.