Cuda Performance

Review Checklist

• Are global memory loads and stores coalesced?
• Is shared memory reducing expensive global traffic or enabling meaningful reuse?
• Are shared memory bank conflicts present?
• Is synchronization within the block justified and minimized?
• Is occupancy limited by registers, shared memory, or launch configuration?
• Is warp divergence hurting throughput?
• Are atomics, reductions, or serialization points on the hot path?
• Is register pressure preventing useful parallelism?
• Are host-device transfers excessive or poorly overlapped?
• Is the optimization improving total runtime rather than only one kernel metric?

Constraints

• Do not claim performance improvements without profiling or benchmark evidence.
• Do not use shared memory by default if coalesced global access and cache behavior are already sufficient.
• Do not optimize for occupancy alone; verify the actual bottleneck.
• Do not introduce synchronization or shared memory complexity unless the reuse benefit is plausible.
• State tradeoffs in maintainability, numerical behavior, portability, and hardware sensitivity.
• Call out race-condition risks, reduction-order changes, and determinism issues when relevant.

Output

Provide:

• the likely bottleneck
• whether it is memory-bound, compute-bound, or transfer-bound
• the proposed shared-memory, launch, or memory-access optimization
• why it is expected to help
• the main risks or tradeoffs
• the validation plan