Parse and analyze .tel PCB netlist files to extract hardware connectivity (nets, pins, component interconnects, and fanout). Use when a user provides a .tel netlist, asks for hardware connection relationships, wants pin/net tracing, or needs a structured summary (JSON/table) from legacy netlist text.
Use this skill to read .tel netlist files and convert them into structured connectivity data for PCB hardware analysis.
Prefer running the bundled parser script first, then answer circuit-connection questions from the parsed JSON.
.tel file with the script in scripts/parse_tel_netlist.py.summary, nets, and component_to_nets in JSON output.GND, VDD33)From any directory:
python C:/Users/ckdfs/.codex/skills/tel-netlist-reader/scripts/parse_tel_netlist.py <path/to/file.tel>
Custom output path:
python C:/Users/ckdfs/.codex/skills/tel-netlist-reader/scripts/parse_tel_netlist.py <path/to/file.tel> --output <path/to/out.json>
$PACKAGES as component/package metadata and reference designator groups.$NETS as logical nets with node lists in RefDes.Pin format.Return concise hardware-centric findings:
SWDIO, SWCLK, NRST)For detailed format caveats and examples, see references/tel-format-notes.md.