Check for upstream updates to existing HighTide2 designs and tools, summarize what changed, and apply updates. Use when a design needs to be refreshed, or with no arguments to audit all designs for available updates.
If $ARGUMENTS is empty or all, run the Upstream Audit first. Otherwise, you are updating the design $0 on platform $1 — determine what kind of update is needed by asking the user or inferring from context.
Check all designs and their tool dependencies for upstream changes. Present a summary so the user can decide what's worth updating.
For each design submodule in .gitmodules, compare the pinned commit to upstream HEAD:
# For each submodule path (e.g., designs/src/minimax/dev/repo):
git -C <submodule-path> rev-parse HEAD # our pinned commit
git -C <submodule-path> ls-remote origin HEAD # upstream latest
If the submodule is not initialized, use git ls-remote with the URL from and compare against the commit recorded in the superproject:
.gitmodulesgit ls-submodule <submodule-path> # pinned commit in superproject
git ls-remote <url> HEAD # upstream latest
For each submodule that has new commits upstream, summarize:
git log --oneline <pinned>..origin/HEAD (or the GitHub API via gh api) to show a summary of what changed. Categorize as:
For each design with a setup.sh, check pinned tool versions against latest:
designs/src/liteeth/dev/setup.sh): check if the pinned commit is behind the upstream default branchpyyaml==6.0.2): check PyPI for newer versionsSummarize each with the same minor/moderate/major classification.
Check OpenROAD-flow-scripts for upstream updates:
git -C OpenROAD-flow-scripts log --oneline HEAD..origin/main | head -20
Summarize the nature of ORFS changes (new features, bug fixes, platform updates, etc.).
Format the results as a table:
| Design/Tool | Pinned | Upstream | Behind | Last Activity | Severity | Recommendation |
|--------------------|------------|------------|--------|---------------|----------|--------------------|
| minimax | abc1234 | def5678 | 12 | 2026-02-15 | Moderate | Bug fixes, review |
| liteeth | ef5f9ee | 1a2b3c4 | 45 | 2026-03-10 | Major | New features |
| verilog-lfsr | 789abcd | 789abcd | 0 | 2025-01-03 | - | Up to date |
| litex (pip) | a25eeec | b36ff0d | 8 | 2026-03-12 | Minor | Docs only |
| ORFS | v3.0-... | v3.1-... | 200+ | 2026-03-14 | Major | Platform updates |
Let the user decide which updates to apply. Small changes that don't affect RTL generation (docs, tests, CI) are usually not worth updating for. Major changes that affect RTL output, fix synthesis bugs, or add new features are worth considering.
Update the submodule to the desired commit:
cd designs/src/$0/dev/repo
git fetch origin
git checkout <new-commit-or-tag>
cd /home/mrg/HighTide2
Check if setup.sh needs changes:
designs/src/$0/dev/setup.shsetup.sh accordinglyRegenerate RTL:
# Clean old dev artifacts
make DESIGN_CONFIG=./designs/$1/$0/config.mk clean_design
# Regenerate
make DESIGN_CONFIG=./designs/$1/$0/config.mk dev
Check for new or changed memories:
designs/$1/$0/sram/ or other designs like NyuziProcessor/liteethconfig.mk ADDITIONAL_LEFS and ADDITIONAL_LIBS if new FakeRAM files were addedPromote release RTL:
cp designs/src/$0/dev/generated/$0.v designs/src/$0/$0.v
(Adjust the path based on where the design's verilog.mk expects release RTL)
Check if verilog.mk needs updates:
designs/src/$0/verilog.mkTest the flow:
make DESIGN_CONFIG=./designs/$1/$0/config.mk
Read current setup.sh:
designs/src/$0/dev/setup.shUpdate version numbers or URLs as needed (e.g., JDK version, pip package commits, sbt version)
Clean old tool artifacts:
# Remove cached tool installations and generated files
rm -rf designs/src/$0/dev/generated
rm -rf designs/src/$0/dev/.venv # if Python-based
rm -rf designs/src/$0/dev/sbt # if sbt-based
rm -rf designs/src/$0/dev/sv2v # if sv2v-based
Regenerate:
make DESIGN_CONFIG=./designs/$1/$0/config.mk dev
Verify RTL matches or update release copy if the generated Verilog changed.
Read current config:
designs/$1/$0/config.mkdesigns/$1/$0/constraint.sdcreports/$1/$0/base/ if availableCongestion troubleshooting priority: It is preferable to keep cell utilization high. If there are congestion problems, try these before lowering utilization:
io.tcl to spread pins and reduce congestion near IO (see designs/asap7/gemmini/io.tcl for reference). Set IO_CONSTRAINTS and FOOTPRINT_TCL in config.mk.MACRO_PLACE_HALO — increase spacing around macros to give the router more room (e.g., 5 5 or 6 6).PLACE_PINS_ARGS = -min_distance <N> -min_distance_in_tracks to spread auto-placed pins.CORE_UTILIZATION or PLACE_DENSITY.Common adjustments in config.mk:
CORE_UTILIZATION — Prefer keeping this high; only lower as a last resort for congestionPLACE_DENSITY — Affects routing congestion (0.6-0.8 typical)CORE_AREA / DIE_AREA — For explicit die size control instead of utilization-basedPLACE_DENSITY_LB_ADDON — Additional placement density lower boundMACRO_PLACE_HALO — Spacing around macros (increase if DRC errors or congestion near macros)ABC_AREA = 1 — Optimize for area in synthesisSYNTH_HIERARCHICAL = 1 — For large designs that need hierarchical synthesisCommon adjustments in constraint.sdc:
clk_io_pct) — Adjust input/output timing marginTest:
make DESIGN_CONFIG=./designs/$1/$0/config.mk clean_all
make DESIGN_CONFIG=./designs/$1/$0/config.mk
Identify memory modules in the design's Verilog that should be black-boxed:
Create LEF and LIB files for each memory:
fakeram_<width>x<depth>_<ports>.{lef,lib}designs/$1/$0/sram/lef/ and designs/$1/$0/sram/lib/Update config.mk to reference the new FakeRAM files:
export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/*.lef
export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/*.lib
export GDS_ALLOW_EMPTY = fakeram*
export MACRO_PLACE_HALO = 5 5
Ensure verilog.mk does not include the memory module source so synthesis instantiates the black-box macro instead.
Create the platform directory:
mkdir -p designs/<new-platform>/$0
Copy and adapt from an existing platform:
config.mk — Change PLATFORM, adjust utilization/density for the new technologyconstraint.sdc — Adjust clock period for the technology nodesram/ — Create platform-specific FakeRAM files if needed (different metal stacks and design rules per platform)Platform-specific clock period guidance:
Test the new platform:
make DESIGN_CONFIG=./designs/<new-platform>/$0/config.mk
./runorfs_ni.sh prefix when running flows non-interactively (e.g., from Claude Code). The regular runorfs.sh uses docker run -it which requires an interactive terminal.{logs,objects,reports,results}/$1/$0/base/clean_all before a full re-run if config.mk or constraint.sdc changed significantly.