Generate, read, validate, and explain electronic circuit diagrams in SchemaText — a plain-text schematic notation using bracket components [R1], power symbols (┯/┷), gate glyphs, and a structured NETLIST section. Trigger whenever the user wants to: draw an electronic circuit as embeddable text (chat, Slack, email, docs, source control); create a text-based or ASCII schematic; validate or debug a SchemaText diagram's connections; read or interpret a circuit diagram in any format; or generate a SchemaText NETLIST for a circuit. Trigger even without the "SchemaText" name — "text schematic", "ASCII circuit", "plain text diagram", "paste into Slack/email", "sketch this circuit", or "write out the schematic" all apply when the subject is an electronic circuit. Does NOT apply to: SPICE simulation files; EDA exports (KiCad, Eagle); software flowcharts; pure calculation scripts; or circuit theory Q&A with no diagram output.
SchemaText is a constrained plain-text notation for electronic schematics — not freehand ASCII art. Its key rule is that topology (what connects to what) is encoded precisely through character adjacency: a terminal is connected only if a wire character directly touches the terminal glyph. Visual proximity is not connection.
The full specification lives in references/schematext-spec.txt. Read it when
you need details on specific component symbols or notation rules. The summary
below covers the rules that matter most for generation.
Contact rule (§4.4): A terminal is wired only if a wire character directly touches the terminal glyph on the correct side. A single space breaks the connection. This is the most common failure mode — don't eyeball it.
Power and ground symbols (§3):
┯ sits at the TOP of a supply line; the wire hangs down from it.┷ sits at the BOTTOM of a return path; the wire connects up to it.--┷┯--Correct: Wrong:
┯ --┷ ┯--
|
[R1]
|
┷
┯ and ┷ are used for ALL power rails and grounds (VDD, VCC, +5V, GND,
0V, VSS…). Never use port-style labels like VDD>--- for a supply rail —
that syntax is for signal ports only.Port tagging (§5):
IN>---- — the name is on the LEFT, > marks the entry, dashes
extend to the right into the circuit. Inputs always enter from the left.----<OUT — dashes extend from the circuit, < marks the
exit, name is on the RIGHT. Outputs always exit to the right.----<IN and OUT>---- are both wrong.Layout — horizontal first (§4.5): For passive (2-terminal) chains, use horizontal layout by default. Reserve vertical orientation for transistors, where the side-entry gate is cleaner than a gate above or below.
Horizontal voltage divider (preferred):
VIN>--[ R1 ]--+--[ R2 ]--+
| |
+---<VOUT ┷
Note the + at every branch point — junctions must be marked even when the wire
continues in the same direction (§4.2).
Centering (§6.0): For vertical 3-terminal components, the drain/source axis
runs through the center character of the bracket. For [ Q1] (5 chars:
[, , Q, 1, ]), the axis column is Q. Every |, ▼, ┷, and ┯
on that axis must land on the exact same column — count characters, don't
estimate.
Gate glyphs (§6.3): ╢ left of bracket = gate enters from left; ╟ right
of bracket = gate exits right. Always separate gate wire from bracket with