Hls Cpp To Rtl

Code Structure

• Use static arrays for memory inference
• Avoid dynamic memory allocation
• Structure loops for pipeline optimization
• Use ap_int/ap_uint for arbitrary precision

Key Pragmas

• #pragma HLS PIPELINE II=1 - Pipeline loops for throughput
• #pragma HLS UNROLL factor=N - Unroll loops for parallelism
• #pragma HLS ARRAY_PARTITION - Memory partitioning
• #pragma HLS DATAFLOW - Task-level parallelism
• #pragma HLS INTERFACE - Port protocol specification

Interface Synthesis

• AXI4-Lite: Control registers and scalar arguments
• AXI4 Memory-Mapped: Large data arrays
• AXI4-Stream: Streaming data interfaces
• ap_none/ap_vld/ap_hs: Simple handshake protocols

Optimization Flow

1. Baseline functional implementation
2. Analyze synthesis report
3. Identify bottleneck (II, latency, resources)
4. Apply targeted optimizations
5. Iterate until QoR targets met

Dependencies

• Vitis HLS CLI awareness
• C/C++ language expertise
• FPGA resource understanding