Fpga Build

Located in vivado/:

Running a build

# From Vivado TCL console:
cd c:/projects/silicontoai/vivado
source build_system_zynq.tcl

Or batch mode:

vivado -mode batch -source vivado/build_system_zynq.tcl

3. Build Outputs

Arty A7 Core

• Bitstream: vivado/build_core_arty/npu_core.bit
• Utilization: Check vivado/build_core_arty/reports/utilization.rpt

Zynq System

• Bitstream: vivado/build_system_zynq/npu_system.bit
• ILA probes: 14 signals, depth 1024
• Debug signals: (* mark_debug = "true" *) annotated in RTL

PYNQ Overlay

• Bitstream: vivado/build_pynq/npu_pynq.bit
• Hardware handoff: vivado/build_pynq/npu_pynq.hwh
• Both .bit and .hwh needed for PYNQ overlay loading

4. FPGA Top Module Descriptions

fpga_core_bringup_top (Arty A7)

• Inputs: board_clk, rst_btn_n, start_btn
• Outputs: alive_led, done_led, debug_led[3:0]
• Self-contained test: PRELOAD → EXECUTE → FLUSH → DRAIN → CHECK
• Expected result: result_match_latched = 1 (LED on)
• Test: Weight=1 × Act=[0..15] → golden = 120 per column

fpga_system_bringup_top (Zynq)

• Full AXI-Lite path: Self-Test FSM → MMIO Bridge → NPU System → Local BRAM
• 16-state FSM orchestrates: DMA weight → swap → preload → DMA act → swap → execute → drain → check
• AXI-Lite write/read drivers included
• (* mark_debug *) on key signals for ILA probing

fpga_pynq_top (PYNQ-Z2)

• PS7 ARM Cortex-A9 → AXI-Lite slave → Register map → NPU system
• Register map at 0x00-0x7C (see header comment in fpga_pynq_top.sv)
• Drain capture with 2-cycle pipeline for BRAM latency
• LED: heartbeat, dma_done, npu_done, drain_valid
• Local test BRAM (512 × 128b) with initialized weight/activation data

5. Register Map (PYNQ)

6. PYNQ Host Notebook

from pynq import Overlay

overlay = Overlay("npu_pynq.bit")
npu = overlay.npu_system

# Write DMA config
npu.write(0x08, 0x31)  # target=weight, mode=preload, acc_clear
npu.write(0x0C, 0x0000)  # src_addr_lo
npu.write(0x14, (1 << 8) | 15)  # total_bursts=1, burst_len=15

# Start DMA
npu.write(0x00, 0x01)

# Poll until done
while not (npu.read(0x04) & 0x1):
    pass

See: host/pynq_npu_demo.ipynb for complete demo.

7. Interpreting Results

Utilization Report

Key resources to monitor:

• LUT: Systolic array MAC logic
• BRAM: SRAM banks + accumulator buffer
• DSP: MAC PE multiply-accumulate (256 DSP slices ideal)
• FF: Pipeline registers

Timing Report

• Check WNS (Worst Negative Slack): Must be ≥ 0 ns
• Check WHS (Worst Hold Slack): Must be ≥ 0 ns
• Critical path usually through systolic array or accumulator