Policy rules, prerequisite definitions, phase gate criteria, feedback loop classification, and checklists for the Phase 4→5 pipeline. Pure reference — no orchestration.
Lower phases MUST NOT violate upper phase specifications: Spec → Architecture → μArch → RTL → Verification RTL must faithfully implement the μArch design. Verification must validate against the original Spec.
Phase 4 reads Phase 1-3 documents as input context. Phase 5 reads Phase 4 artifacts.
No agent needs to "remember" another agent's output — it reads the document.
State is persisted at .rat/state/rat-p4p5-impl-verify-state.json for resumability.
Phase 4→5 transition requires BOTH:
Quality Gate verdicts: PASS or FAIL + findings[]
Before each phase, verify required upstream files exist:
Specific file lists are defined inline in each orchestrator's phase steps.
After Phase 5 Final Compliance Gate PASS, generate summary, then STOP. Do NOT proceed to Phase 6.
| Artifact | Required Check |
|---|---|
docs/phase-3-uarch/*.md | At least one μArch module spec exists |
reviews/phase-3-uarch/uarch-review.md | File exists AND contains Verdict: PASS |
docs/phase-1-research/requirements.json | File exists (needed for traceability) |
docs/phase-1-research/io_definition.json | File exists (needed for port verification) |
refc/*/*.c | At least one C reference model source exists |
docs/phase-3-uarch/phase-3-summary.md | File exists (Phase 3 summary for context) |
docs/phase-3-uarch/phase-3-summary.mddocs/phase-3-uarch/{module}.md for each modulereviews/phase-3-uarch/uarch-review.md verdict=PASSreviews/phase-3-uarch/feature-preservation.md.rat/state/{module}-phase-3-complete.jsonArtifact Gate:
Quality Gate:
reviews/phase-4-rtl/functional-completeness.md, reviews/phase-4-rtl/design-review.mdreviews/phase-4-rtl/lint-report.mdSummary Validation: docs/phase-4-rtl/phase-4-summary.md must exist
Artifact Gate: all verification sub-phases (5a-5e) pass Quality Gate:
reviews/phase-5-verify/requirement-traceability.mdreviews/phase-5-verify/final-compliance.md, reviews/phase-5-verify/e2e-traceability.mdSummary Validation: docs/phase-5-verify/phase-5-summary.md must exist
Stream B artifacts generated concurrently with Stream A (RTL implementation):
docs/phase-4-rtl/stream-b-sva-skeletons.mddocs/phase-4-rtl/stream-b-cdc-preliminary.mddocs/phase-4-rtl/stream-b-tb-skeletons.mdTraceability Convention:
// Source: docs/phase-3-uarch/{module}.md, Section: {section}# REQ-{NNN}: {description}Merge Point: Stream A (lint-clean + unit PASS) + Stream B artifacts ready → Phase 4→5 Gate.
| Type | Scope | Handling | Re-verify |
|---|---|---|---|
| UNIT_FIX | Single module (SVA fail, assertion error) | rtl-p4s-bugfix (parallel across modules) | Only failed sub-phases |
| INTEGRATION_FIX | Cross-module interface | rtl-p4s-bugfix (sequential) | 5b + 5c |
| DESIGN_FIX | Architecture-level | IMMEDIATE STOP → user approval | All (5a-5e) after upper phase fix |
Batch UNIT_FIX across sub-phases:
Max 2 feedback loops per sub-phase. After loop 2 fails → escalate to user.
| Fix Type | Re-run Sub-phases | Condition |
|---|---|---|
| UNIT_FIX (SVA fail) | 5a only (formal) | SVA property affected |
| UNIT_FIX (sim fail) | 5c only (integration) | Testbench affected |
| INTEGRATION_FIX | 5b + 5c (CDC + integration) | Interface modified |
| DESIGN_FIX | All (5a-5e) after upper phase approval | Architecture changed |
{
"loop_count": 1,
"max_loops": 2,
"failures": [{
"sub_phase": "5a",
"type": "UNIT_FIX",
"module": "example_module",
"description": "SVA counterexample at cycle 42",
"fix_applied": "Added pipeline register",
"re_run_phases": ["5a"]
}],
"status": "in_progress"
}
After each successful feedback fix:
docs/lessons-learned.md with format: LL-{NNN} with sections: Symptom, Root Cause, Fix Applied, Prevention, Related (REQ IDs, module, fix commit, ADR, Phase 5 Sub-phase)All phases must enforce:
i_, o_, io_ (NOT suffix). Clock/reset exemptclk (single) or {domain}_clk (multiple). Reset: rst_n or {domain}_rst_nlogic only (no reg/wire), always_ff/always_comb, ANSI port styleu_, generate prefix: gen_