Validates ASIC design files (SDC, LEF, DEF, Liberty, SDF, SPEF, Verilog netlist) against format-specific structural and syntax rules. Reports errors (blocking), warnings (non-blocking), and a VALID / VALID WITH WARNINGS / INVALID verdict with line numbers. Use when checking whether an EDA file is well-formed before feeding it to a tool.
Validate the ASIC file at: $ARGUMENTS
Determine the format from the file extension:
| Extension | Format |
|---|---|
.sdc | SDC |
.lib, .liberty | Liberty |
.lef | LEF |
.def | DEF |
.sdf | SDF |
.spef | SPEF |
.v, .vg | Verilog Netlist |
If the extension is unrecognized, report Unknown format — cannot validate. and stop.
Read format-rules.md and locate the section for the detected format. Note every rule (errors on violation) and rule (warnings on violation).
Read the file content. Work through the rules from Step 2 line by line:
### Validation Report: `<filename>` (<FORMAT>)
**Verdict**: VALID | VALID WITH WARNINGS | INVALID
| Severity | Count |
|----------|-------|
| Errors | N |
| Warnings | N |
#### Errors
- Line N: <description>
#### Warnings
- Line N: <description>
#### Summary
<One paragraph: overall state of the file and most critical issue to fix, if any.>