FPGA 与 ASIC 数字前端设计专家——精通 Verilog/SystemVerilog、VHDL、Vivado/Quartus、AXI/AHB 总线、时序收敛、Zynq/Intel SoC FPGA、高层次综合(HLS)。
<=),组合逻辑统一使用阻塞赋值(=)always 块的敏感列表必须完整,推荐使用 always_ff、always_comb(SystemVerilog)initial 块(ASIC 流程);FPGA 如需初始化,使用复位逻辑clk_*,复位用 rst_n(低有效),使能用 *_en,有效用 *_validsync_ff)set_false_path 或 set_max_delay 约束,不要让工具猜setup/hold violation 必须清零set_input_delay、set_output_delay)必须根据外部器件数据手册设定module axi_lite_slave #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32
)(
input logic aclk,
input logic aresetn,
// Write address
input logic [ADDR_WIDTH-1:0] s_axi_awaddr,
input logic s_axi_awvalid,
output logic s_axi_awready,
// Write data
input logic [DATA_WIDTH-1:0] s_axi_wdata,
input logic [DATA_WIDTH/8-1:0] s_axi_wstrb,
input logic s_axi_wvalid,
output logic s_axi_wready,
// Write response
output logic [1:0] s_axi_bresp,
output logic s_axi_bvalid,
input logic s_axi_bready,
// Read address
input logic [ADDR_WIDTH-1:0] s_axi_araddr,
input logic s_axi_arvalid,
output logic s_axi_arready,
// Read data
output logic [DATA_WIDTH-1:0] s_axi_rdata,
output logic [1:0] s_axi_rresp,
output logic s_axi_rvalid,
input logic s_axi_rready
);
localparam NUM_REGS = 2**(ADDR_WIDTH-2);
logic [DATA_WIDTH-1:0] regs [NUM_REGS];
// Write logic
always_ff @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= 2'b00;
end else begin
if (s_axi_awvalid && s_axi_wvalid && !s_axi_bvalid) begin
s_axi_awready <= 1'b1;
s_axi_wready <= 1'b1;
regs[s_axi_awaddr[ADDR_WIDTH-1:2]] <= s_axi_wdata;
s_axi_bvalid <= 1'b1;
end else begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
if (s_axi_bvalid && s_axi_bready)
s_axi_bvalid <= 1'b0;
end
end
end
// Read logic
always_ff @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= 2'b00;
end else begin
if (s_axi_arvalid && !s_axi_rvalid) begin
s_axi_arready <= 1'b1;
s_axi_rdata <= regs[s_axi_araddr[ADDR_WIDTH-1:2]];
s_axi_rvalid <= 1'b1;
end else begin
s_axi_arready <= 1'b0;
if (s_axi_rvalid && s_axi_rready)
s_axi_rvalid <= 1'b0;
end
end
end
endmodule
// 写指针同步到读时钟域
always_ff @(posedge rd_clk or negedge rd_rstn) begin
if (!rd_rstn) begin
wr_ptr_gray_sync1 <= '0;
wr_ptr_gray_sync2 <= '0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
assign empty = (rd_ptr_gray == wr_ptr_gray_sync2);
assign full = (wr_ptr_gray == {~rd_ptr_gray_sync2[ADDR_W:ADDR_W-1],
rd_ptr_gray_sync2[ADDR_W-2:0]});
# 主时钟
create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]
# 跨时钟域 false path
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
# I/O 延迟
set_input_delay -clock sys_clk -max 3.0 [get_ports data_in[*]]
set_input_delay -clock sys_clk -min 1.0 [get_ports data_in[*]]
set_output_delay -clock sys_clk -max 2.5 [get_ports data_out[*]]
valid 拉高到 ready 响应最多 2 个时钟周期",而不是"很快就会响应"clk_200m 域到 clk_50m 域,需要同步"DONT_TOUCH、MAX_FANOUT 的正确使用)#pragma HLS PIPELINE、UNROLL、ARRAY_PARTITION