Master coordinator for complete T180 (180nm) IO Ring generation. Handles signal classification, device mapping, pin configuration, JSON generation, and complete workflow through DRC/LVS verification. Use this skill for any T180 IO Ring generation task. Trigger when user mentions T180, 180nm, 180nm IO ring, or any IO ring task targeting the 180nm process node.
You are the master coordinator for T180 (180nm) IO Ring generation. You handle the entire workflow as a single skill — from parsing requirements through DRC/LVS verification.
SCRIPTS_PATH="/absolute_path/to/io-ring-orchestrator-T180/scripts"
# Verify:
ls "$SCRIPTS_PATH/validate_intent.py" || echo "ERROR: SCRIPTS_PATH not found"
output_dir exactly once per run and reuse it for all Step 2-12 artifacts.timestamp after Step 0.AMS_OUTPUT_ROOT once in Step 0 so script-level outputs remain deterministic.Required conventions:
AMS_OUTPUT_ROOT: workspace-level output rootoutput_dir: per-run directory under ${AMS_OUTPUT_ROOT}/generated/${timestamp}${AMS_OUTPUT_ROOT} and its fixed subdirs (drc, lvs)# Resolve stable workspace root (prefer AMS_IO_AGENT_PATH, fallback to current directory)
if [ -n "${AMS_IO_AGENT_PATH:-}" ]; then
WORK_ROOT="${AMS_IO_AGENT_PATH}"
else
WORK_ROOT="$(pwd)"
fi
# Unified output root for script-level artifacts (DRC/LVS/PEX/screenshots fallback)
export AMS_OUTPUT_ROOT="${WORK_ROOT}/output"
mkdir -p "${AMS_OUTPUT_ROOT}/generated"
# Create per-run directory once and reuse it across all steps
if [ -n "${output_dir:-}" ] && [ -d "${output_dir}" ]; then
echo "Reusing existing output_dir: ${output_dir}"
else
timestamp="${timestamp:-$(date +%Y%m%d_%H%M%S)}"
output_dir="${AMS_OUTPUT_ROOT}/generated/${timestamp}"
fi
mkdir -p "$output_dir"
echo "AMS_OUTPUT_ROOT=${AMS_OUTPUT_ROOT}"
echo "output_dir=${output_dir}"
Parse user input: signal list, ring dimensions (chip_width × chip_height), pad counts per side, placement order, voltage domain specifications.
Apply this step only when image input is provided.
Rules:
references/image_vision_instruction.md first.PFILLER* devicesBuild a draft JSON with only structural fields. No device/pin/corner inference in this step.
Primary reference:
references/draft_builder_T180.mdProcess:
placement_order/dimensions/counts cannot be uniquely resolved, ask the user directly, then continue.ring_config.instances for pad with only:namepositiontype{output_dir}/io_ring_intent_graph_draft.json.Strict boundary:
device, pin_connection, direction, domain, view_name, or any corner instance in Step 2.Read the Step 2 draft and enrich in a single pass.
Mandatory inputs for Step 3:
Input precedence:
ring_config, name, position, type) unless a hard inconsistency is reported.Primary reference:
references/enrichment_rules_T180.mdProcess:
ring_config and all draft instances (name, position, type) and user prompt constraints.device based on device selection tables.direction for digital IO (PDDW0412SCDG only).pin_connection according to the Pin Configuration Matrix.domain, view_name, pad_width, pad_height.PCORNER) at correct transition positions.references/enrichment_rules_T180.md:{output_dir}/io_ring_intent_graph.json.Handoff rule:
Before Step 5 validation, explicitly verify Step 3 output against references:
references/enrichment_rules_T180.md -> Classification Priority, Domain Isolation, Voltage Domain Logicreferences/enrichment_rules_T180.md -> Analog Pin Configuration, Digital Pin Configuration, Corner Rulesreferences/enrichment_rules_T180.md -> Direction Rules, Pin-Family Gate, VSS-Consistency GateAlso verify that Step 3 output preserves explicit constraints from the original user prompt (especially voltage-domain assignments, provider names, and direction overrides).
If any gate fails, repair JSON first and repeat Step 4. Do not proceed to Step 5.
python3 $SCRIPTS_PATH/validate_intent.py {output_dir}/io_ring_intent_graph.json
references/draft_builder_T180.md or references/enrichment_rules_T180.md).Validation repair constraints:
ring_config, name, position, type) during repair.python3 $SCRIPTS_PATH/build_confirmed_config.py \
{output_dir}/io_ring_intent_graph.json \
{output_dir}/io_ring_confirmed.json \
--skip-editor
Note: build_confirmed_config.py is hardcoded for T180 — no process node parameter needed.
python3 $SCRIPTS_PATH/generate_schematic.py \
{output_dir}/io_ring_confirmed.json \
{output_dir}/io_ring_schematic.il
python3 $SCRIPTS_PATH/generate_layout.py \
{output_dir}/io_ring_confirmed.json \
{output_dir}/io_ring_layout.il
Note: Both scripts are hardcoded for T180 — no process node parameter needed.
python3 $SCRIPTS_PATH/check_virtuoso_connection.py
python3 $SCRIPTS_PATH/run_il_with_screenshot.py \
{output_dir}/io_ring_schematic.il \
{lib} {cell} \
{output_dir}/schematic_screenshot.png \
schematic
python3 $SCRIPTS_PATH/run_il_with_screenshot.py \
{output_dir}/io_ring_layout.il \
{lib} {cell} \
{output_dir}/layout_screenshot.png \
layout
python3 $SCRIPTS_PATH/run_drc.py {lib} {cell} layout T180
io_ring_intent_graph.json), then re-run Step 6-10 to regenerate and recheck.python3 $SCRIPTS_PATH/run_lvs.py {lib} {cell} layout T180
Provide structured summary:
These rules apply to every step of the process and cannot be overridden.
PCORNER instances at the exact transition points between sides (Top/Right/Bottom/Left) during placement. Do not append them at the end.VIOH*, GIOH*, VPST, GPST), use Voltage Domain devices (PVDD2CDG/PVSS2CDG). Priority 2 (Explicit): If user mentions "voltage domain". Otherwise, default to Regular Power/Ground (PVDD1CDG/PVSS1CDG).GIOLA) unless specific rules override.final_answer() until all verification steps (DRC/LVS) are complete and successful.PCORNER pads inserted at all 4 corners?pin_connection labels match the Pin Configuration Matrix exactly?GIOLA (or equivalent)?| Problem | Solution |
|---|---|
| Scripts not found | Use absolute path; verify with ls $SCRIPTS_PATH/validate_intent.py |
| Virtuoso not connected | Start Virtuoso; do NOT retry SKILL execution |
| Domain isolation fails | Re-classify signals using ring-wrap continuity, ensure analog/digital domains are separated |
| Voltage domain continuity fails | Check VDDPST/VSSPST labels — pads with different labels belong to different voltage domains; ensure BLANK is inserted between them and each domain block has its own provider pair |
| Missing BLANK between domains | Adjacent pads with different VDDPST/VSSPST labels need BLANK separator; check auto_filler logic |
| Validation failure | Enter Step 5 repair loop: parse error -> query matching rule in references -> apply targeted JSON fix -> re-validate |
| DRC failure | Enter Step 10 repair loop: parse DRC report -> query matching reference rules -> fix intent JSON -> regenerate and rerun DRC |
| LVS failure | Enter Step 11 repair loop: parse LVS mismatch -> return to Step 3 to check/fix intent JSON -> rerun Step 3-11 |
Repair loop cap (applies to Step 10/11):
io-ring-orchestrator-T180/
├── SKILL.md # This file
├── requirements.txt # Python requirements (minimal)
│
├── scripts/ # CLI entry point scripts (each self-contained)
│ ├── validate_intent.py
│ ├── build_confirmed_config.py
│ ├── generate_schematic.py
│ ├── generate_layout.py
│ ├── check_virtuoso_connection.py
│ ├── run_il_with_screenshot.py
│ ├── run_drc.py
│ ├── run_lvs.py
│ └── README.md
│
├── references/ # Documentation & templates
│ ├── draft_builder_T180.md
│ ├── enrichment_rules_T180.md
│ ├── T180_Technology.md
│ └── image_vision_instruction.md
│
└── assets/ # All bundled code (self-contained)
├── core/ # Core logic
│ ├── layout/ # Layout generation modules
│ │ ├── config/lydevices_180.json
│ │ ├── layout_generator_factory.py
│ │ ├── process_node_config.py
│ │ ├── device_classifier.py
│ │ ├── position_calculator.py
│ │ ├── layout_validator.py
│ │ ├── filler_generator.py
│ │ ├── voltage_domain.py
│ │ ├── editor_confirm_merge.py
│ │ └── editor_utils.py
│ ├── schematic/
│ │ └── devices/
│ │ └── IO_decive_info_T180_parser.py
│ └── intent_graph/
│ └── json_validator.py
│
├── device_info/ # Device templates
│ ├── IO_device_info_T180.json
│ └── IO_decive_info_T180_parser.py
│
└── external_scripts/ # External executables
└── calibre/
└── T180/