Policy rules, phase gate definitions, cascading quality protocol, handoff checklist, and ADR requirements for the Phase 1→3 pipeline. Pure reference — no orchestration.
Lower phases MUST NOT violate upper phase specifications: Spec → Architecture → μArch Each phase strictly adheres to decisions made in all preceding phases. Deletion, reduction, or modification of features for convenience is FORBIDDEN. If a change is needed, control returns to the upper phase for approval.
Higher abstraction levels demand MORE iterative refinement. Dynamic convergence with graduated minimums: Phase 1 (Research): min 3 rounds (chief-coordinated, fixed — P1 is the quality foundation) Phase 2 (Architecture): min 2, max 5 rounds — memory, performance, ref model consistency Phase 3 (μArch): min 2, max 5 rounds — performance, interface, memory optimization
P2/P3 use convergence criteria (finding_delta < 0.1, critical resolved, wonder stable). Principle: refine thoroughly at the top, execute efficiently at the bottom.
Design artifacts serve as persistent memory. Each phase reads upstream documents and writes
downstream documents. State at .rat/state/rat-p1p3-spec-uarch-state.json.
Every phase transition requires BOTH:
Before each phase, verify required upstream files exist (specific file lists defined inline in orchestrator steps).
During iterative review rounds:
.rat/scratch/phase-{N}/round-{R}-{agent}.md
Coordinator reads all round files to aggregate feedback.
On phase gate PASS: consolidated review saved to reviews/, scratch cleaned.
After Phase 3 Quality Gate PASS, generate summary + ADR, then STOP. Do NOT proceed to Phase 4.
Artifact Gate: requirements.json + io_definition.json + timing_constraints.json + domain-analysis.md exist Quality Gate:
reviews/phase-1-research/research-review.mdreviews/phase-1-research/research-review-r1.md, r2.md, r3.md (mandatory)docs/phase-1-research/ambiguity-assessment.md exists with per-axis scoresSummary Validation: docs/phase-1-research/phase-1-summary.md
Artifact Gate: architecture.md (with D2 block diagram) + refc//.c exist Quality Gate:
reviews/phase-2-architecture/feature-coverage.mddocs/phase-2-architecture/wonder-log.md)reviews/phase-2-architecture/architecture-review-r1.md, r2.md (minimum), additional rounds if neededreviews/phase-2-architecture/architecture-review.mdPhase 2 Iterative Review (dynamic convergence, coordinated by rtl-architect):
Summary + ADR: phase-2-summary.md + 3-5 ADRs in docs/decisions/
Artifact Gate: docs/phase-3-uarch/*.md + bfm/ directory exist Quality Gate:
reviews/phase-3-uarch/feature-preservation.mddocs/phase-3-uarch/wonder-log.md)docs/phase-3-uarch/upstream-feedback-report.md)reviews/phase-3-uarch/uarch-review-r1.md, r2.md (minimum), additional rounds if neededreviews/phase-3-uarch/uarch-review.mdPhase 3 Iterative Review (dynamic convergence, coordinated by rtl-architect):
Summary + ADR: phase-3-summary.md + 3-5 ADRs in docs/decisions/
P1 → P2 → P3: Each phase reads upstream artifacts, writes downstream.
When P3 discovers P1 requirement gaps:
requirement-delta.md (Step 4.5 of spec-to-uarch-orchestrator)upper_spec_blocking: true
b. User is consulted via AskUserQuestion
c. If user approves revision: P1 re-runs with delta as input
d. P2 re-runs reading updated P1 artifacts
e. P3 re-runs reading updated P2 artifactsAfter feedback loop iteration:
Review rounds within P2 and P3 use dynamic convergence instead of fixed 3 rounds:
| Parameter | Value | Rationale |
|---|---|---|
| min_rounds | 2 | Minimum for meaningful review |
| max_rounds | 5 | Prevent infinite loops |
| finding_delta_threshold | 0.1 | < 10% new findings = stable |
| critical_resolution | ALL | All Critical/High must be resolved |
| wonder_stability | true | No new High-risk assumptions |
docs/phase-3-uarch/phase-3-summary.mddocs/phase-3-uarch/{module}.md for each modulereviews/phase-3-uarch/uarch-review.md verdict=PASSreviews/phase-3-uarch/feature-preservation.md.rat/state/{module}-phase-3-complete.jsoni_, o_, io_. Clock: {domain}_clk. Reset: {domain}_rst_nsnake_case or ALL_CAPS only. Parameters ALL_CAPS, localparam L_ prefixu_, generate gen_, logic only