LDO Skill — PTM 180nm Low Dropout Regulator

All generated files (logs, plots, netlists) go to WORK/ at the repo root. Override with env-var ANALOG_WORK_DIR.

Task → Script Decision Guide

Running

cd LDO/scripts
python run_ldo.py          # All analyses in parallel (~10 s)

Key outputs in WORK/:

Circuit Topology

PMOS-pass LDO with Miller-compensated two-stage error amplifier.

VIN ──► M2 (pass, PMOS) ──────────────────────────► VOUT
              ▲ gate=net3                              │
              │                                  R0 (R_FB_TOP)
         ┌────┴───────────────────────────┐           │
         │      Error Amplifier           │      net30 (V_fb)
         │                                │           │
         │  M3/M4 (PMOS current mirror)   │      R1 (R_FB_BOT)
         │     ▲             ▲            │           │
         │   M0(VREF)    M1(V_fb)  ←──── ┘          GND
         │   NMOS diff pair (non-inv / inv)
         │        │
         │   M5 (tail mirror, 10×) ─── M6 (diode ref, 1×) ←── I_bias
         └────────────────────────────────────────────────────────────
Compensation: R2 (R_COMP) + C0 (C_COMP) from net3 → VOUT
  → introduces left-half-plane zero: fz = 1/(2π·R2·C0)
Bypass: C1 (large, ≈1F) on ibias node; C2 (C_OUT) on VOUT

Topology constraints:

• M0 = M1 (identical sizes — matched differential pair)
• M3 = M4 (identical sizes — matched current mirror load)
• M5 / M6: same L, W_M5 = N × W_M6 (mirror ratio N, default N = 10)

Editable globals: all in LDO/scripts/ldo_common.py.

Initial Sizing from Specs

Given user inputs: Vref, Vin, Vout, Iload, Cload (default 1 µF).

Step 1 — Feedback Resistors R0, R1

From regulation condition Vout = Vref × (R0 + R1) / R1:

R0 / R1 = Vout/Vref − 1

Select I_div = 1% × Iload   (current through divider)
→ R0 + R1 = Vout / I_div = Vout × 100 / Iload
→ R1 = Vref / I_div
→ R0 = (Vout − Vref) / I_div

Step 2 — Pass Transistor M2 (PMOS)

M2 must supply full Iload. Start with minimum L for low Vdrop:

Total W = 10 × 10 × 100 × Wmin = 22 mm. DC iteration rule (see Step 7): adjust multiplier to achieve Vout accuracy ±1%.

Step 3 — Bias Current Mirror M5 / M6 (NMOS)

Ibias = Iload / 1000          (e.g. 100 µA for Iload = 100 mA)
I_tail = Ibias × N_mirror     (default N = 10, so I_tail = Iload/100)

Large L reduces current mismatch (ΔI/I ∝ 1/L for channel-length modulation). Bypass capacitor on ibias node: C1 = 1 F (large ideal cap, suppresses AC ripple).

Step 4 — Differential Pair M0 / M1 (NMOS, matched)

Long L for high intrinsic gain (gm·ro) and good matching:

Step 5 — Current Mirror Load M3 / M4 (PMOS, matched)

Very long L for high ro (high Av1) and good matching:

Step 6 — Compensation Network

Cc = Cload / 5000              (initial value; adjust for stability)
Rz: choose so that ωz ≈ GBW  (see Stability section below)

Set C_COMP = Cc, R_COMP = Rz in ldo_common.py.

Step 7 — DC Output Voltage Accuracy Check (iterate)

Run python run_ldo_dc.py. Requirement: |Vout_sim − Vout_target| / Vout_target ≤ 1%.

Theoretical Formulas

Key Small-Signal Quantities

β  = R1 / (R0 + R1) = Vref / Vout      (feedback factor)
Av1 = gm1 × (ro1 ∥ ro3)                (error-amp DC gain)
gm  = √(2 · µ · Cox · W/L · Id)        → adjust mainly via W; L if needed
ro  ∝ 1 / (λ · Id)                     → adjust via L (longer L → larger ro)

Closed-Loop Specs

Loop Gain (DC):

T0 = β × Av1 × gm2 × ro2

GBW (Gain-Bandwidth Product):

GBW ≈ β × gm1 / Cc

Load Regulation (output impedance at low freq):

Zout(s) ≈ (1 + s·Cc·(ro1∥ro3)) / (β · Av1 · gm2)

PSRR (supply rejection):

PSRR(s) ≈ [gm2·(ro1∥ro3)·s·Cc + 1/ro2] / (β · Av1 · gm2)

Poles and Zero

where CS = (Cn·Cc·CL) / (Cn·Cc + Cn·CL + Cc·CL), Cn = gate cap of M2.

Stability target: ωz ≈ GBW and ωp3 ≥ 2 × GBW.

Noise (Output-Referred)

Thermal noise:

Vn²_out = (1/β²) × [4kT(R0∥R1) + 8kTγ·(gm1 + gm4) / gm1²]

1/f (flicker) noise (dominant at low frequency):

Vn²_out = (2K / β²·Cox·f) × [1/(W1·L1) + (1/(W4·L4))·(gm4/gm1)²]
         ≈ (2K / β²·Cox·f) × [1/(W1·L1) + µp·L1/(µn·W1·L4²)]

Low-frequency: 1/f noise dominates. High-frequency: thermal noise dominates; compare relative magnitudes.

Spec Optimization Guide

Output Voltage Accuracy (±1%)

Primary knob: M2 multiplier (fingers).

Re-run run_ldo_dc.py after each change.

Load Regulation

Zout(s) ≈ (1 + s·Cc·(ro1∥ro3)) / (β · Av1 · gm2)

Line Regulation

Phase Margin (Stability)

Target: PM ≥ 45° (≥ 60° recommended). Tune ωz and ωp3.

Reading the Bode plot (loop gain phase vs frequency):

• Phase has a gradual slope ("缓坡") region caused by ωz.
• ωz should align with the GBW crossing.
  • Cue: if the slope ends at too high a frequency → increase Rz.
  • Cue: if the slope ends at too low a frequency → decrease Rz.

PSRR

PSRR ≈ [gm2·(ro1∥ro3)·s·Cc + 1/ro2] / (β · Av1 · gm2)

Noise

Offset

Primary rule: ↑W1 and ↑L4 simultaneously reduce both offset and noise.

Trade-off Analysis

Inspect simulation results: identify which spec has the least margin (closest to failing) and which has excess margin before adjusting.

Decision workflow:

1. Run run_ldo.py, read ldo_report.txt.
2. List all specs with margin sign and magnitude.
3. Pick the worst (most over-spec or most under-margin).
4. Choose the adjustment that fixes it without pushing a near-failing spec into failure.
5. Re-run and iterate.

Transistor Size Variables (ldo_common.py)

Output File Conventions

• All outputs to WORK/ — never inside the skill package.
• Matplotlib Agg backend — never pop up figures; always plt.close(fig) after savefig().
• Forward slashes in ngspice paths (spath() helper).
• Parallel execution via ThreadPoolExecutor for independent simulations.
• Max 3 vertically stacked subplots per figure.

References