Use when developing Verilog/SystemVerilog on a remote Linux server with VCS and viewing waveforms locally in VS Code with VaporView. First copy from example template, then modify per design.
Run VCS simulations on a remote Linux server and view waveforms locally in VS Code using VaporView plugin. Always copy from the verified example template first, then modify for your design.
Remote (Linux server):
Local (Windows/macOS):
The example template at ~/agent_digits/example/vcs/ is a verified, working reference. Always copy from it to avoid build errors.
# On remote server — copy entire vcs directory
ssh user@server "cd /project && cp -r ~/agent_digits/example/vcs/ ./vcs_new && cd vcs_new && rm -rf simv* csrc* DVEfiles AN.DB *.fsdb *.log *.vpd *.key *.vdb ucli.key verdi_config_file wave.fsdb wave.vcd"
scp your_design.v your_tb.v user@server:/project/vcs_new/
Change RTL, TB, and TOP to match your design:
ssh user@server "cd /project/vcs_new && sed -i 's/shift_reg_16bit.v/your_design.v/g; s/tb_shift_reg.v/your_tb.v/g; s/tb_shift_reg/your_tb_module/g' Makefile"
ssh user@server "echo 'your_design.v
your_tb.v' > /project/vcs_new/filelist.f"
ssh user@server "cd /project/vcs_new && make clean && make"
vcs/
├── Makefile # Compile + run commands
├── filelist.f # File list for Verdi
├── design.v # RTL design files
├── tb_design.v # Testbench files
├── simv # Generated simulation binary
├── simv.daidir/ # Generated simulation data
├── csrc/ # Generated C source
├── wave.fsdb # FSDB waveform (Verdi)
└── wave.vcd # VCD waveform (VaporView)
Makefile — Verified template# Makefile for VCS Simulation
# VCS + Verdi flow
# *** CHANGE THESE per design ***
RTL = your_design.v
TB = your_tb.v
TOP = your_tb_module
# VCS options
VCS = vcs
VCS_FLAGS = -full64 -sverilog -debug_access+all -kdb
# Verdi PLI (use absolute path)
VERDI_PLI = /opt/synopsys/verdi/V-2023.12/share/PLI/VCS/LINUX64
# Simulation executable
SIMV = simv
# Waveform file
WAVE = wave.fsdb
# Default target: compile and run