Use when you want to run VCS simulation, DC synthesis, and FM formal verification as a team workflow (serial: VCS → DC → FM). Includes memory checkpoint mechanism for crash recovery.
Run a 3-agent team to execute the full EDA flow in serial order: VCS (verify RTL) → DC (synthesize) → FM (formal verify). Each agent uses its own skill and writes a memory checkpoint on completion, so the flow can resume from any point after a crash.
Step 1 Step 2 Step 3
┌─────────┐ ┌──────────┐ ┌──────────────┐
│ VCS │────▶│ DC │──────▶│ FM │
│ Simulate│ │ Synthesize│ │ Formal Verify │
└────┬────┘ └────┬─────┘ └──────┬───────┘
│ │ │
▼ ▼ ▼
CHECKPOINT 1 CHECKPOINT 2 CHECKPOINT 3
(memory) (memory) (memory)
Each checkpoint is written to the project memory system. On crash/restart, read the latest checkpoint to know exactly where to resume.
C:\Users\$USER\.claude\projects\D--claudecode-digits\memory\eda-progress-{project}.md with type project---