Eda Team Flow

EDA Team Flow: VCS → DC → FM Serial Workflow with Checkpoints

Overview

Run a 3-agent team to execute the full EDA flow in serial order: VCS (verify RTL) → DC (synthesize) → FM (formal verify). Each agent uses its own skill and writes a memory checkpoint on completion, so the flow can resume from any point after a crash.

Why Serial (Not Parallel)

1. RTL consistency: VCS must verify RTL first; if DC finds RTL issues and fixes them, VCS must re-run with the same fixed RTL
2. No resource contention: DC uses 16 cores + heavy memory; VCS also needs significant resources
3. No license conflict: Both use Synopsys licenses
4. Clean dependency chain: VCS passes → DC synthesizes verified RTL → FM verifies DC output

Architecture