Policy rules, mandatory sequence, parallel UNIT_FIX decision tree, escalation rules, and checklists for the RTL bug fix workflow. Pure reference — no orchestration.
verilator --lint-only -Wall (max 3 lint rounds)Each step can only proceed after the previous step is complete. Lint is a necessary condition, NOT sufficient — simulation is required.
| Failure Pattern | Handling | Parallelism |
|---|---|---|
| Different modules, UNIT_FIX | Parallel rtl-p4s-bugfix, one per module | run_in_background: true |
| Same module, multiple failures |
| Sequential within single task |
| No |
| INTEGRATION_FIX (cross-module) | Always sequential | No |
| Mixed UNIT_FIX + INTEGRATION_FIX | INTEGRATION_FIX first, then UNIT_FIX in parallel | Partial |
Verification-done marker created ONLY after ALL parallel fixes pass functional verification.
| Fix Type | After Fix | Re-verify |
|---|---|---|
| UNIT_FIX (SVA fail) | lint → unit TB → unit sim | Only affected Phase 5 sub-phase |
| UNIT_FIX (sim fail) | lint → unit TB → unit sim | Only affected Phase 5 sub-phase |
| INTEGRATION_FIX | lint → unit TB + integration TB → sim | 5b + 5c |
In feedback mode: lesson-learned recording is mandatory (not just recommended).
dut.sys_clk, dut.sys_rst_n (clock/reset)dut.i_*, dut.o_* (input/output ports)ls sim/*/test_*.py sim/*/tb_*.sv 2>/dev/nullIntegration bugs (multi-module):
When regression suite available:
Compound mode bugs (e.g., MODE_RECON):